The present invention generally relates to instructing methods and execution systems, and more particularly to an instructing method which specifies an instruction which is to be executed in an information processing apparatus and an execution system for executing an instruction in the information processing apparatus.
Recently, the performance of a processor improved considerably owing to improvements in the integration density of semiconductor devices and operation speeds of the semiconductor devices. However, there is a demand to further improve the performance of the processor. In order to meet this demand, an architecture called reduced instruction set computer (RISC) has been proposed. According to this RISC, an instruction word has a fixed length of 32 bits and the operation is carried out only between registers. In addition, a memory access is restricted only to a transfer between a memory and a register, and the RISC only has instructions with a high frequency of use of programs. By the restrictions described above, it is possible to simplify the hardware which is required to execute the instructions and also simplify the control of the hardware. Hence, the performance of the processor can be improved by increasing the operation clock frequency and reducing the number of cycles required to execute one instruction. On the other hand, there are proposals to simultaneously execute a plurality of instructions so as to further improve the performance of the processor.
FIGS. 1A, 1B and 1C show examples of instruction formats used in the conventional RISC architecture.
FIG. 1A shows an instruction having a first format. Based on an instruction code OP, this instruction instructs an operation between a register content specified by a second register instruction field R2X and a register content specified by a third register instruction field R3X and a storage of an operation result in a register specified by a first register instruction field R1X.
FIG. 1B shows an instruction having a second format. When this instruction is an operation instruction, this instruction instructs an operation between the register content specified by the second register instruction field R2X and 16-bit immediate data IMM16 and a storage of an operation result in the register specified by the first register instruction field R1X. On the other hand, when this instruction is a load instruction, this instruction instructs an addition of an address which is the register content specified by the second register instruction field R2X and a deviation or offset which is given as the immediate data IMM16 and a storage of the data of the address of the memory obtained by the addition in the register specified by the first register specifying field R1X.
FIG. 1C shows an instruction having a third format. This instruction instructs a storage of a 21-bit immediate data IMM21 in the register specified by the first register specifying field R1X.
According to the instruction having the first format, the twenty-first through thirty-first bits are unused and there is a problem in that the bit utilization efficiency is poor. On the other hand, according to the instruction having the second format, there is a problem in that a plurality of instructions must be used when large immediate data and deviation are required, such as the case where the immediate data exceeds 16 bits. Similarly, according to the instruction having the third format, there is a problem in that a plurality of instructions must be used when a large immediate data is required, such as the case where the immediate data exceeds 21 bits.
Furthermore, when executing a plurality of instructions in parallel, the control hardware becomes complex and the scale of the hardware structure required to execute the instructions in parallel becomes large because there exist a large number of combinations of instructions which must be executed in parallel.